WDT_RST_EN=dis, WDT_INT_EN=dis, RST_LATE_VAL=wdt2pow31, RST_EARLY_VAL=wdt2pow31, EN=dis, INT_LATE=inactive, INT_LATE_VAL=wdt2pow31, INT_EARLY=inactive, RST_EARLY=noEvent, WIN_EN=dis, RST_LATE=noEvent, INT_EARLY_VAL=wdt2pow31
Watchdog Timer Control Register.
| INT_LATE_VAL | Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 (wdt2pow31): 2**31 clock cycles. 1 (wdt2pow30): 2**30 clock cycles. 2 (wdt2pow29): 2**29 clock cycles. 3 (wdt2pow28): 2**28 clock cycles. 4 (wdt2pow27): 2^27 clock cycles. 5 (wdt2pow26): 2**26 clock cycles. 6 (wdt2pow25): 2**25 clock cycles. 7 (wdt2pow24): 2**24 clock cycles. 8 (wdt2pow23): 2**23 clock cycles. 9 (wdt2pow22): 2**22 clock cycles. 10 (wdt2pow21): 2**21 clock cycles. 11 (wdt2pow20): 2**20 clock cycles. 12 (wdt2pow19): 2**19 clock cycles. 13 (wdt2pow18): 2**18 clock cycles. 14 (wdt2pow17): 2**17 clock cycles. 15 (wdt2pow16): 2**16 clock cycles. |
| RST_LATE_VAL | Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 (wdt2pow31): 2**31 clock cycles. 1 (wdt2pow30): 2**30 clock cycles. 2 (wdt2pow29): 2**29 clock cycles. 3 (wdt2pow28): 2**28 clock cycles. 4 (wdt2pow27): 2^27 clock cycles. 5 (wdt2pow26): 2**26 clock cycles. 6 (wdt2pow25): 2**25 clock cycles. 7 (wdt2pow24): 2**24 clock cycles. 8 (wdt2pow23): 2**23 clock cycles. 9 (wdt2pow22): 2**22 clock cycles. 10 (wdt2pow21): 2**21 clock cycles. 11 (wdt2pow20): 2**20 clock cycles. 12 (wdt2pow19): 2**19 clock cycles. 13 (wdt2pow18): 2**18 clock cycles. 14 (wdt2pow17): 2**17 clock cycles. 15 (wdt2pow16): 2**16 clock cycles. |
| EN | Windowed Watchdog Timer Enable. 0 (dis): Disable. 1 (en): Enable. |
| INT_LATE | Windowed Watchdog Timer Interrupt Flag Too Late. 0 (inactive): No interrupt is pending. 1 (pending): An interrupt is pending. |
| WDT_INT_EN | Windowed Watchdog Timer Interrupt Enable. 0 (dis): Disable. 1 (en): Enable. |
| WDT_RST_EN | Windowed Watchdog Timer Reset Enable. 0 (dis): Disable. 1 (en): Enable. |
| INT_EARLY | Windowed Watchdog Timer Interrupt Flag Too Soon. 0 (inactive): No interrupt is pending. 1 (pending): An interrupt is pending. |
| INT_EARLY_VAL | Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 (wdt2pow31): 2**31 clock cycles. 1 (wdt2pow30): 2**30 clock cycles. 2 (wdt2pow29): 2**29 clock cycles. 3 (wdt2pow28): 2**28 clock cycles. 4 (wdt2pow27): 2^27 clock cycles. 5 (wdt2pow26): 2**26 clock cycles. 6 (wdt2pow25): 2**25 clock cycles. 7 (wdt2pow24): 2**24 clock cycles. 8 (wdt2pow23): 2**23 clock cycles. 9 (wdt2pow22): 2**22 clock cycles. 10 (wdt2pow21): 2**21 clock cycles. 11 (wdt2pow20): 2**20 clock cycles. 12 (wdt2pow19): 2**19 clock cycles. 13 (wdt2pow18): 2**18 clock cycles. 14 (wdt2pow17): 2**17 clock cycles. 15 (wdt2pow16): 2**16 clock cycles. |
| RST_EARLY_VAL | Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 (wdt2pow31): 2**31 clock cycles. 1 (wdt2pow30): 2**30 clock cycles. 2 (wdt2pow29): 2**29 clock cycles. 3 (wdt2pow28): 2**28 clock cycles. 4 (wdt2pow27): 2^27 clock cycles. 5 (wdt2pow26): 2**26 clock cycles. 6 (wdt2pow25): 2**25 clock cycles. 7 (wdt2pow24): 2**24 clock cycles. 8 (wdt2pow23): 2**23 clock cycles. 9 (wdt2pow22): 2**22 clock cycles. 10 (wdt2pow21): 2**21 clock cycles. 11 (wdt2pow20): 2**20 clock cycles. 12 (wdt2pow19): 2**19 clock cycles. 13 (wdt2pow18): 2**18 clock cycles. 14 (wdt2pow17): 2**17 clock cycles. 15 (wdt2pow16): 2**16 clock cycles. |
| CLKRDY_IE | Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. |
| CLKRDY | Clock Status. |
| WIN_EN | Enables the Windowed Watchdog Function. 0 (dis): Windowed Mode Disabled (i.e. Compatibility Mode). 1 (en): Windowed Mode Enabled. |
| RST_EARLY | Windowed Watchdog Timer Reset Flag Too Soon. 0 (noEvent): The event has not occurred. 1 (occurred): The event has occurred. |
| RST_LATE | Windowed Watchdog Timer Reset Flag Too Late. 0 (noEvent): The event has not occurred. 1 (occurred): The event has occurred. |