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Maxim-Integrated /max78002 /GCR /MEMCTRL

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Interpret as MEMCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FWS0 (SYSRAM0ECC)SYSRAM0ECC

Description

Memory Clock Control Register.

Fields

FWS

Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
SYSRAM0ECC

SYSRAM0 ECC Select.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk