Maxim-Integrated /max78002 /I2S /CTRL0CH0

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Interpret as CTRL0CH0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSB_FIRST)LSB_FIRST 0 (PDM_FILT)PDM_FILT 0 (PDM_EN)PDM_EN 0 (USEDDR)USEDDR 0 (PDM_INV)PDM_INV 0CH_MODE 0 (WS_POL)WS_POL 0 (MSB_LOC)MSB_LOC 0 (ALIGN)ALIGN 0 (EXT_SEL)EXT_SEL 0STEREO 0WSIZE 0 (TX_EN)TX_EN 0 (RX_EN)RX_EN 0 (FLUSH)FLUSH 0 (RST)RST 0 (FIFO_LSB)FIFO_LSB 0RX_THD_VAL

Description

Global mode channel.

Fields

LSB_FIRST

LSB Transmit Receive First.

PDM_FILT

PDM Filter.

PDM_EN

PDM Enable.

USEDDR

DDR.

PDM_INV

Invert PDM.

CH_MODE

SCK Select.

WS_POL

WS polarity select.

MSB_LOC

MSB location.

ALIGN

Align to MSB or LSB.

EXT_SEL

External SCK/WS selection.

STEREO

Stereo mode of I2S.

WSIZE

Data size when write to FIFO.

TX_EN

TX channel enable.

RX_EN

RX channel enable.

FLUSH

Flushes the TX/RX FIFO buffer.

RST

Write 1 to reset channel.

FIFO_LSB

Bit Field Control.

RX_THD_VAL

depth of receive FIFO for threshold interrupt generation.

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