Maxim-Integrated /max78002 /LPGCR /PCLKDIS

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Interpret as PCLKDIS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)GPIO2 0 (WDT1)WDT1 0 (TMR4)TMR4 0 (TMR5)TMR5 0 (UART3)UART3 0 (LPCOMP)LPCOMP

GPIO2=en

Description

Low Power Peripheral Clock Disable Register.

Fields

GPIO2

Low Power GPIO 2 Clock Disable.

0 (en): enable it.

1 (dis): disable it.

WDT1

Low Power Watchdog 1 Clock Disable.

TMR4

Low Power Timer 4 Clock Disable.

TMR5

Low Power Timer 5 Clock Disable.

UART3

Low Power UART 3 Clock Disable.

LPCOMP

Low Power Comparator Clock Disable.

Links

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