TOD_ALARM=inactive, SQW_SEL=freq1Hz, TOD_ALARM_IE=dis, RDY_IE=dis, EN=dis, WR_EN=inactive, SSEC_ALARM=inactive, RDY=busy, BUSY=idle, SSEC_ALARM_IE=dis, SQW_EN=inactive
RTC Control Register.
| EN | Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| TOD_ALARM_IE | Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| SSEC_ALARM_IE | Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| BUSY | RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 0 (idle): Idle. 1 (busy): Busy. |
| RDY | RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 0 (busy): Register has not updated. 1 (ready): Ready. |
| RDY_IE | RTC Ready Interrupt Enable. 0 (dis): Disable. 1 (en): Enable. |
| TOD_ALARM | Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| SSEC_ALARM | Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| SQW_EN | Square Wave Output Enable. 0 (inactive): Not active 1 (Pending): Active |
| SQW_SEL | Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 0 (freq1Hz): 1 Hz (Compensated). 1 (freq512Hz): 512 Hz (Compensated). 2 (freq4KHz): 4 KHz. 3 (clkDiv8): RTC Input Clock / 8. |
| RD_EN | Asynchronous Counter Read Enable. |
| WR_EN | Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 0 (inactive): Not active 1 (Pending): Active |