Application Interrupt and Reset Control Register
| VECTCLRACTIVE | Set this bit to 1 will clears all active state information for fixed and configurable exceptions. The bit is a write only bit and can only be written when the core is halted. Note: It is the debugger’s responsibility to re-initialize the stack. |
| SYSRESETREQ | Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested. The bit is a write only bit and self-clears as part of the reset sequence. |
| VECTORKEY | When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. |