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Nuvoton /NUC1xx_registers /SCS /NVIC_ICPR

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Interpret as NVIC_ICPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLRPEND

Description

IRQ0 ~ IRQ31 Clear-Pending Control Register

Fields

CLRPEND

Writing 1 to a bit un-pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data