Regviz

Nuvoton /NUC1xx_registers /SCS /NVIC_ISPR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as NVIC_ISPR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Nuvoton/M05x_registers/SCS/NVIC_ISPR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SETPEND

Description

IRQ0 ~ IRQ31 Set-Pending Control Register

Fields

SETPEND

Writing 1 to a bit pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data