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Nuvoton /NUC1xx_registers /SPI0 /SPI_VARCLK

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Interpret as SPI_VARCLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VARCLK

Description

Variable Clock Pattern Register

Fields

VARCLK

Variable Clock Pattern The value in this field is the frequency patterns of the SPI clock. If the bit patterns of VARCLK are 0, the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are 1, the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data