RISC-V /Debug /Access Register

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Interpret as Access Register

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0regno0 (arg0)write 0 (disabled)transfer 0 (disabled)postexec 0 (disabled)aarpostincrement 0aarsize 0cmdtype

transfer=disabled, postexec=disabled, write=arg0, aarpostincrement=disabled

Description

This command gives the debugger access to CPU registers and allows it to execute the Program Buffer. It performs the following sequence of operations:

  1. If {accessregister-write} is clear and {accessregister-transfer} is set, then copy data from the register specified by {accessregister-regno} into the arg0 region of data, and perform any side effects that occur when this register is read from M-mode.
  2. If {accessregister-write} is set and {accessregister-transfer} is set, then copy data from the arg0 region of data into the register specified by {accessregister-regno}, and perform any side effects that occur when this register is written from M-mode.
  3. If {accessregister-aarpostincrement} and {accessregister-transfer} are set, increment {accessregister-regno}. {accessregister-regno} may also be incremented if {accessregister-aarpostincrement} is set and {accessregister-transfer} is clear.
  4. Execute the Program Buffer, if {accessregister-postexec} is set.

If any of these operations fail, {abstractcs-cmderr} is set and none of the remaining steps are executed. An implementation may detect an upcoming failure early, and fail the overall command before it reaches the step that would cause failure. If the failure is that the requested register does not exist in the hart, {abstractcs-cmderr} must be set to 3 (exception).

Debug Modules must implement this command and must support read and write access to all GPRs when the selected hart is halted. Debug Modules may optionally support accessing other registers, or accessing registers when the hart is running. It is recommended that if one register in a group is accessible, then all registers in that group are accessible, but each individual register (aside from GPRs) may be supported differently across read, write, and halt status.

Registers might not be accessible if they wouldn’t be accessible by M mode code currently running. (E.g. fflags might not be accessible when mstatus.FS is 0.) If this is the case, the debugger is responsible for changing state to make the registers accessible. The Core Debug Registers (debreg) should be accessible if abstract CSR access is implemented.

Abstract Register Numbers

Numbers Group Description
0x0000 – 0x0fff CSRs. The ``PC’’ can be accessed here through {csr-dpc}.
0x1000 – 0x101f GPRs
0x1020 – 0x103f Floating point registers
0xc000 – 0xffff Reserved for non-standard extensions and internal use.
📌 NOTE

The encoding of {accessregister-aarsize} was chosen to match {sbcs-sbaccess} in {dm-sbcs}.

This command modifies arg0 only when a register is read. The other data registers are not changed.

Fields

regno

Number of the register to access, as described in tab:regno. {csr-dpc} may be used as an alias for PC if this command is supported on a non-halted hart.

write

When {accessregister-transfer} is set:

0 (arg0): Copy data from the specified register into arg0 portion of data.

1 (register): Copy data from arg0 portion of data into the specified register.

transfer

0 (disabled): Don’t do the operation specified by {accessregister-write}.

1 (enabled): Do the operation specified by {accessregister-write}.

postexec

0 (disabled): No effect. This variant must be supported, and is the only supported one if {abstractcs-progbufsize} is 0.

1 (enabled): Execute the program in the Program Buffer exactly once after performing the transfer, if any. Supporting this variant is optional.

aarpostincrement

0 (disabled): No effect. This variant must be supported.

1 (enabled): After a successful register access, {accessregister-regno} is incremented. Incrementing past the highest supported value causes {accessregister-regno} to become UNSPECIFIED. Supporting this variant is optional. It is undefined whether the increment happens when {accessregister-transfer} is 0.

aarsize

2 (32bit): Access the lowest 32 bits of the register.

3 (64bit): Access the lowest 64 bits of the register.

4 (128bit): Access the lowest 128 bits of the register.

cmdtype

This is 0 to indicate Access Register Command.

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