Regviz

STMicroelectronics /STM32F072x /ADC /CHSELR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CHSELR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32F030/ADC/CHSELR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHSEL0)CHSEL0 0 (CHSEL1)CHSEL1 0 (CHSEL2)CHSEL2 0 (CHSEL3)CHSEL3 0 (CHSEL4)CHSEL4 0 (CHSEL5)CHSEL5 0 (CHSEL6)CHSEL6 0 (CHSEL7)CHSEL7 0 (CHSEL8)CHSEL8 0 (CHSEL9)CHSEL9 0 (CHSEL10)CHSEL10 0 (CHSEL11)CHSEL11 0 (CHSEL12)CHSEL12 0 (CHSEL13)CHSEL13 0 (CHSEL14)CHSEL14 0 (CHSEL15)CHSEL15 0 (CHSEL16)CHSEL16 0 (CHSEL17)CHSEL17 0 (CHSEL18)CHSEL18

Description

channel selection register

Fields

CHSEL0

Channel-x selection
CHSEL1

Channel-x selection
CHSEL2

Channel-x selection
CHSEL3

Channel-x selection
CHSEL4

Channel-x selection
CHSEL5

Channel-x selection
CHSEL6

Channel-x selection
CHSEL7

Channel-x selection
CHSEL8

Channel-x selection
CHSEL9

Channel-x selection
CHSEL10

Channel-x selection
CHSEL11

Channel-x selection
CHSEL12

Channel-x selection
CHSEL13

Channel-x selection
CHSEL14

Channel-x selection
CHSEL15

Channel-x selection
CHSEL16

Channel-x selection
CHSEL17

Channel-x selection
CHSEL18

Channel-x selection

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data