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STMicroelectronics /STM32F072x /RCC /BDCR

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Interpret as BDCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSEON)LSEON 0 (LSERDY)LSERDY 0 (LSEBYP)LSEBYP 0LSEDRV 0RTCSEL 0 (RTCEN)RTCEN 0 (BDRST)BDRST

Description

Backup domain control register (RCC_BDCR)

Fields

LSEON

External Low Speed oscillator enable
LSERDY

External Low Speed oscillator ready
LSEBYP

External Low Speed oscillator bypass
LSEDRV

LSE oscillator drive capability
RTCSEL

RTC clock source selection
RTCEN

RTC clock enable
BDRST

Backup domain software reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data