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STMicroelectronics /STM32F072x /TSC /IOCCR

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Interpret as IOCCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (G1_IO1)G1_IO1 0 (G1_IO2)G1_IO2 0 (G1_IO3)G1_IO3 0 (G1_IO4)G1_IO4 0 (G2_IO1)G2_IO1 0 (G2_IO2)G2_IO2 0 (G2_IO3)G2_IO3 0 (G2_IO4)G2_IO4 0 (G3_IO1)G3_IO1 0 (G3_IO2)G3_IO2 0 (G3_IO3)G3_IO3 0 (G3_IO4)G3_IO4 0 (G4_IO1)G4_IO1 0 (G4_IO2)G4_IO2 0 (G4_IO3)G4_IO3 0 (G4_IO4)G4_IO4 0 (G5_IO1)G5_IO1 0 (G5_IO2)G5_IO2 0 (G5_IO3)G5_IO3 0 (G5_IO4)G5_IO4 0 (G6_IO1)G6_IO1 0 (G6_IO2)G6_IO2 0 (G6_IO3)G6_IO3 0 (G6_IO4)G6_IO4

Description

I/O channel control register

Fields

G1_IO1

G1_IO1 channel mode
G1_IO2

G1_IO2 channel mode
G1_IO3

G1_IO3 channel mode
G1_IO4

G1_IO4 channel mode
G2_IO1

G2_IO1 channel mode
G2_IO2

G2_IO2 channel mode
G2_IO3

G2_IO3 channel mode
G2_IO4

G2_IO4 channel mode
G3_IO1

G3_IO1 channel mode
G3_IO2

G3_IO2 channel mode
G3_IO3

G3_IO3 channel mode
G3_IO4

G3_IO4 channel mode
G4_IO1

G4_IO1 channel mode
G4_IO2

G4_IO2 channel mode
G4_IO3

G4_IO3 channel mode
G4_IO4

G4_IO4 channel mode
G5_IO1

G5_IO1 channel mode
G5_IO2

G5_IO2 channel mode
G5_IO3

G5_IO3 channel mode
G5_IO4

G5_IO4 channel mode
G6_IO1

G6_IO1 channel mode
G6_IO2

G6_IO2 channel mode
G6_IO3

G6_IO3 channel mode
G6_IO4

G6_IO4 channel mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data