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STMicroelectronics /STM32F100xx /FSMC /BWTR4

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Interpret as BWTR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDSET0ADDHLD0DATAST0CLKDIV0DATLAT0ACCMOD

Description

SRAM/NOR-Flash write timing registers 4

Fields

ADDSET

ADDSET
ADDHLD

ADDHLD
DATAST

DATAST
CLKDIV

CLKDIV
DATLAT

DATLAT
ACCMOD

ACCMOD

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data