STMicroelectronics /STM32F100xx /GPIOA /CRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MODE0 0CNF0 0MODE1 0CNF1 0MODE2 0CNF2 0MODE3 0CNF3 0MODE4 0CNF4 0MODE5 0CNF5 0MODE6 0CNF6 0MODE7 0CNF7

Description

Port configuration register low (GPIOn_CRL)

Fields

MODE0

Port n.0 mode bits

CNF0

Port n.0 configuration bits

MODE1

Port n.1 mode bits

CNF1

Port n.1 configuration bits

MODE2

Port n.2 mode bits

CNF2

Port n.2 configuration bits

MODE3

Port n.3 mode bits

CNF3

Port n.3 configuration bits

MODE4

Port n.4 mode bits

CNF4

Port n.4 configuration bits

MODE5

Port n.5 mode bits

CNF5

Port n.5 configuration bits

MODE6

Port n.6 mode bits

CNF6

Port n.6 configuration bits

MODE7

Port n.7 mode bits

CNF7

Port n.7 configuration bits

Links

()