STMicroelectronics /STM32F101xx /GPIOA /BSRR

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Interpret as BSRR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BS0)BS0 0 (BS1)BS1 0 (BS2)BS2 0 (BS3)BS3 0 (BS4)BS4 0 (BS5)BS5 0 (BS6)BS6 0 (BS7)BS7 0 (BS8)BS8 0 (BS9)BS9 0 (BS10)BS10 0 (BS11)BS11 0 (BS12)BS12 0 (BS13)BS13 0 (BS14)BS14 0 (BS15)BS15 0 (BR0)BR0 0 (BR1)BR1 0 (BR2)BR2 0 (BR3)BR3 0 (BR4)BR4 0 (BR5)BR5 0 (BR6)BR6 0 (BR7)BR7 0 (BR8)BR8 0 (BR9)BR9 0 (BR10)BR10 0 (BR11)BR11 0 (BR12)BR12 0 (BR13)BR13 0 (BR14)BR14 0 (BR15)BR15

Description

Port bit set/reset register (GPIOn_BSRR)

Fields

BS0

Set bit 0

BS1

Set bit 1

BS2

Set bit 1

BS3

Set bit 3

BS4

Set bit 4

BS5

Set bit 5

BS6

Set bit 6

BS7

Set bit 7

BS8

Set bit 8

BS9

Set bit 9

BS10

Set bit 10

BS11

Set bit 11

BS12

Set bit 12

BS13

Set bit 13

BS14

Set bit 14

BS15

Set bit 15

BR0

Reset bit 0

BR1

Reset bit 1

BR2

Reset bit 2

BR3

Reset bit 3

BR4

Reset bit 4

BR5

Reset bit 5

BR6

Reset bit 6

BR7

Reset bit 7

BR8

Reset bit 8

BR9

Reset bit 9

BR10

Reset bit 10

BR11

Reset bit 11

BR12

Reset bit 12

BR13

Reset bit 13

BR14

Reset bit 14

BR15

Reset bit 15

Links

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