STMicroelectronics /STM32F102xx /GPIOA /BRR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BRR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BR0)BR0 0 (BR1)BR1 0 (BR2)BR2 0 (BR3)BR3 0 (BR4)BR4 0 (BR5)BR5 0 (BR6)BR6 0 (BR7)BR7 0 (BR8)BR8 0 (BR9)BR9 0 (BR10)BR10 0 (BR11)BR11 0 (BR12)BR12 0 (BR13)BR13 0 (BR14)BR14 0 (BR15)BR15

Description

Port bit reset register (GPIOn_BRR)

Fields

BR0

Reset bit 0

BR1

Reset bit 1

BR2

Reset bit 1

BR3

Reset bit 3

BR4

Reset bit 4

BR5

Reset bit 5

BR6

Reset bit 6

BR7

Reset bit 7

BR8

Reset bit 8

BR9

Reset bit 9

BR10

Reset bit 10

BR11

Reset bit 11

BR12

Reset bit 12

BR13

Reset bit 13

BR14

Reset bit 14

BR15

Reset bit 15

Links

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