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STMicroelectronics /STM32F730 /C_ADC /CSR

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Interpret as CSR

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31282724232019161512118743000000000000000000000000000000000000000000 (AWD1)AWD10 (EOC1)EOC10 (JEOC1)JEOC10 (JSTRT1)JSTRT10 (STRT1)STRT10 (OVR1)OVR10 (AWD2)AWD20 (EOC2)EOC20 (JEOC2)JEOC20 (JSTRT2)JSTRT20 (STRT2)STRT20 (OVR2)OVR20 (AWD3)AWD30 (EOC3)EOC30 (JEOC3)JEOC30 (JSTRT3)JSTRT30 (STRT3)STRT30 (OVR3)OVR3

Description

ADC Common status register

Fields

AWD1

Analog watchdog flag of ADC 1
EOC1

End of conversion of ADC 1
JEOC1

Injected channel end of conversion of ADC 1
JSTRT1

Injected channel Start flag of ADC 1
STRT1

Regular channel Start flag of ADC 1
OVR1

Overrun flag of ADC 1
AWD2

Analog watchdog flag of ADC 2
EOC2

End of conversion of ADC 2
JEOC2

Injected channel end of conversion of ADC 2
JSTRT2

Injected channel Start flag of ADC 2
STRT2

Regular channel Start flag of ADC 2
OVR2

Overrun flag of ADC 2
AWD3

Analog watchdog flag of ADC 3
EOC3

End of conversion of ADC 3
JEOC3

Injected channel end of conversion of ADC 3
JSTRT3

Injected channel Start flag of ADC 3
STRT3

Regular channel Start flag of ADC 3
OVR3

Overrun flag of ADC3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data