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STMicroelectronics /STM32F730 /RCC /AHB3LPENR

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Interpret as AHB3LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FMCLPEN)FMCLPEN 0 (QSPILPEN)QSPILPEN

Description

AHB3 peripheral clock enable in low power mode register

Fields

FMCLPEN

Flexible memory controller module clock enable during Sleep mode
QSPILPEN

Quand SPI memory controller clock enable during Sleep mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data