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STMicroelectronics /STM32F730 /SAI1 /BIM

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Interpret as BIM

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVRUDRIE)OVRUDRIE 0 (MUTEDETIE)MUTEDETIE 0 (WCKCFGIE)WCKCFGIE 0 (FREQIE)FREQIE 0 (CNRDYIE)CNRDYIE 0 (AFSDETIE)AFSDETIE 0 (LFSDETIE)LFSDETIE

Description

BInterrupt mask register2

Fields

OVRUDRIE

Overrun/underrun interrupt enable
MUTEDETIE

Mute detection interrupt enable
WCKCFGIE

Wrong clock configuration interrupt enable
FREQIE

FIFO request interrupt enable
CNRDYIE

Codec not ready interrupt enable
AFSDETIE

Anticipated frame synchronization detection interrupt enable
LFSDETIE

Late frame synchronization detection interrupt enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data