STMicroelectronics /STM32F745 /FMC /SDCR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SDCR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NC0NR0MWID 0 (NB)NB 0CAS0 (WP)WP 0SDCLK 0 (RBURST)RBURST 0RPIPE

Description

SDRAM Control Register 2

Fields

NC

Number of column address bits

NR

Number of row address bits

MWID

Memory data bus width

NB

Number of internal banks

CAS

CAS latency

WP

Write protection

SDCLK

SDRAM clock configuration

RBURST

Burst read

RPIPE

Read pipe

Links

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