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STMicroelectronics /STM32F750 /PWR /CSR1

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Interpret as CSR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WUIF)WUIF 0 (SBF)SBF 0 (PVDO)PVDO 0 (BRR)BRR 0 (BRE)BRE 0 (VOSRDY)VOSRDY 0 (ODRDY)ODRDY 0 (ODSWRDY)ODSWRDY 0UDRDY

Description

power control/status register

Fields

WUIF

Wakeup internal flag
SBF

Standby flag
PVDO

PVD output
BRR

Backup regulator ready
BRE

Backup regulator enable
VOSRDY

Regulator voltage scaling output selection ready bit
ODRDY

Over-drive mode ready
ODSWRDY

Over-drive mode switching ready
UDRDY

Under-drive ready flag

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data