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STMicroelectronics /STM32F750 /SPDIF_RX /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXNE)RXNE 0 (CSRNE)CSRNE 0 (PERR)PERR 0 (OVR)OVR 0 (SBD)SBD 0 (SYNCD)SYNCD 0 (FERR)FERR 0 (SERR)SERR 0 (TERR)TERR 0WIDTH5

Description

Status register

Fields

RXNE

Read data register not empty
CSRNE

Control Buffer register is not empty
PERR

Parity error
OVR

Overrun error
SBD

Synchronization Block Detected
SYNCD

Synchronization Done
FERR

Framing error
SERR

Synchronization error
TERR

Time-out error
WIDTH5

Duration of 5 symbols counted with SPDIF_CLK

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data