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STMicroelectronics /STM32F765 /C_ADC /CSR

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Interpret as CSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AWD1)AWD1 0 (EOC1)EOC1 0 (JEOC1)JEOC1 0 (JSTRT1)JSTRT1 0 (STRT1)STRT1 0 (OVR1)OVR1 0 (AWD2)AWD2 0 (EOC2)EOC2 0 (JEOC2)JEOC2 0 (JSTRT2)JSTRT2 0 (STRT2)STRT2 0 (OVR2)OVR2 0 (AWD3)AWD3 0 (EOC3)EOC3 0 (JEOC3)JEOC3 0 (JSTRT3)JSTRT3 0 (STRT3)STRT3 0 (OVR3)OVR3

Description

ADC Common status register

Fields

AWD1

Analog watchdog flag of ADC 1
EOC1

End of conversion of ADC 1
JEOC1

Injected channel end of conversion of ADC 1
JSTRT1

Injected channel Start flag of ADC 1
STRT1

Regular channel Start flag of ADC 1
OVR1

Overrun flag of ADC 1
AWD2

Analog watchdog flag of ADC 2
EOC2

End of conversion of ADC 2
JEOC2

Injected channel end of conversion of ADC 2
JSTRT2

Injected channel Start flag of ADC 2
STRT2

Regular channel Start flag of ADC 2
OVR2

Overrun flag of ADC 2
AWD3

Analog watchdog flag of ADC 3
EOC3

End of conversion of ADC 3
JEOC3

Injected channel end of conversion of ADC 3
JSTRT3

Injected channel Start flag of ADC 3
STRT3

Regular channel Start flag of ADC 3
OVR3

Overrun flag of ADC3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data