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STMicroelectronics /STM32F765 /SDMMC1 /CLKCR

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Interpret as CLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV0 (CLKEN)CLKEN 0 (PWRSAV)PWRSAV 0 (BYPASS)BYPASS 0WIDBUS 0 (NEGEDGE)NEGEDGE 0 (HWFC_EN)HWFC_EN

Description

SDI clock control register

Fields

CLKDIV

Clock divide factor
CLKEN

Clock enable bit
PWRSAV

Power saving configuration bit
BYPASS

Clock divider bypass enable bit
WIDBUS

Wide bus mode enable bit
NEGEDGE

SDIO_CK dephasing selection bit
HWFC_EN

HW Flow Control enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data