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STMicroelectronics /STM32F7x3 /C_ADC /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MULT0DELAY0 (DDS)DDS 0DMA0ADCPRE 0 (VBATE)VBATE 0 (TSVREFE)TSVREFE

Description

ADC common control register

Fields

MULT

Multi ADC mode selection
DELAY

Delay between 2 sampling phases
DDS

DMA disable selection for multi-ADC mode
DMA

Direct memory access mode for multi ADC mode
ADCPRE

ADC prescaler
VBATE

VBAT enable
TSVREFE

Temperature sensor and VREFINT enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data