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STMicroelectronics /STM32F7x3 /I2C1 /TIMINGR

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Interpret as TIMINGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLL0SCLH0SDADEL0SCLDEL0PRESC

Description

Timing register

Fields

SCLL

SCL low period (master mode)
SCLH

SCL high period (master mode)
SDADEL

Data hold time
SCLDEL

Data setup time
PRESC

Timing prescaler

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data