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STMicroelectronics /STM32F7x3 /TIM2 /CCMR1_Output

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Interpret as CCMR1_Output

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CC1S 0 (OC1FE)OC1FE 0 (OC1PE)OC1PE 0OC1M0 (OC1CE)OC1CE 0CC2S 0 (OC2FE)OC2FE 0 (OC2PE)OC2PE 0OC2M0 (OC2CE)OC2CE 0 (OC1M_3)OC1M_3 0 (OC2M_3)OC2M_3

Description

capture/compare mode register 1 (output mode)

Fields

CC1S

CC1S
OC1FE

OC1FE
OC1PE

OC1PE
OC1M

OC1M
OC1CE

OC1CE
CC2S

CC2S
OC2FE

OC2FE
OC2PE

OC2PE
OC2M

OC2M
OC2CE

OC2CE
OC1M_3

Output Compare 1 mode - bit 3
OC2M_3

Output Compare 2 mode - bit 3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data