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STMicroelectronics /STM32F7x5 /FMC /SDTR1

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Interpret as SDTR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TMRD0TXSR0TRAS0TRC0TWR0TRP0TRCD

Description

SDRAM Timing register 1

Fields

TMRD

Load Mode Register to Active
TXSR

Exit self-refresh delay
TRAS

Self refresh time
TRC

Row cycle delay
TWR

Recovery delay
TRP

Row precharge delay
TRCD

Row to column delay

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data