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STMicroelectronics /STM32F7x6 /DCMI /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HSYNC)HSYNC 0 (VSYNC)VSYNC 0 (FNE)FNE

Description

status register

Fields

HSYNC

HSYNC
VSYNC

VSYNC
FNE

FIFO not empty

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data