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STMicroelectronics /STM32F7x6 /RCC /BDCR

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Interpret as BDCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSEON)LSEON 0 (LSERDY)LSERDY 0 (LSEBYP)LSEBYP 0 (RTCSEL0)RTCSEL0 0 (RTCSEL1)RTCSEL1 0 (RTCEN)RTCEN 0 (BDRST)BDRST

Description

Backup domain control register

Fields

LSEON

External low-speed oscillator enable
LSERDY

External low-speed oscillator ready
LSEBYP

External low-speed oscillator bypass
RTCSEL0

RTC clock source selection
RTCSEL1

RTC clock source selection
RTCEN

RTC clock enable
BDRST

Backup domain software reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data