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STMicroelectronics /STM32F7x6 /TIM1 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCPC)CCPC 0 (CCUS)CCUS 0 (CCDS)CCDS 0MMS0 (TI1S)TI1S 0 (OIS1)OIS1 0 (OIS1N)OIS1N 0 (OIS2)OIS2 0 (OIS2N)OIS2N 0 (OIS3)OIS3 0 (OIS3N)OIS3N 0 (OIS4)OIS4

Description

control register 2

Fields

CCPC

Capture/compare preloaded control
CCUS

Capture/compare control update selection
CCDS

Capture/compare DMA selection
MMS

Master mode selection
TI1S

TI1 selection
OIS1

Output Idle state 1
OIS1N

Output Idle state 1
OIS2

Output Idle state 2
OIS2N

Output Idle state 2
OIS3

Output Idle state 3
OIS3N

Output Idle state 3
OIS4

Output Idle state 4

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data