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STMicroelectronics /STM32F7x7 /DSI /DSI_CLCR

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Interpret as DSI_CLCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DPCC)DPCC 0 (ACR)ACR

Description

DSI Host Clock Lane Configuration Register

Fields

DPCC

D-PHY Clock Control
ACR

Automatic Clock lane Control

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data