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STMicroelectronics /STM32F7x7 /DSI /DSI_PUCR

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Interpret as DSI_PUCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (URCL)URCL 0 (UECL)UECL 0 (URDL)URDL 0 (UEDL)UEDL

Description

DSI Host PHY ULPS Control Register

Fields

URCL

ULPS Request on Clock Lane
UECL

ULPS Exit on Clock Lane
URDL

ULPS Request on Data Lane
UEDL

ULPS Exit on Data Lane

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data