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STMicroelectronics /STM32F7x7 /DSI /DSI_WRPCR

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Interpret as DSI_WRPCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLLEN)PLLEN 0NDIV0IDF0ODF0 (REGEN)REGEN

Description

DSI Wrapper Regulator and PLL Control Register

Fields

PLLEN

PLL Enable
NDIV

PLL Loop Division Factor
IDF

PLL Input Division Factor
ODF

PLL Output Division Factor
REGEN

Regulator Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data