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STMicroelectronics /STM32F7x9 /DFSDM /DFSDM_CHCFG0R2

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Interpret as DFSDM_CHCFG0R2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTRBS0OFFSET

Description

DFSDM channel configuration 0 register 2

Fields

DTRBS

Data right bit-shift for channel 0
OFFSET

24-bit calibration offset for channel 0

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data