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STMicroelectronics /STM32G030 /TIM1 /CCMR2_Output

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Interpret as CCMR2_Output

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CC3S 0 (OC3FE)OC3FE 0 (OC3PE)OC3PE 0OC3M0 (OC3CE)OC3CE 0CC4S 0 (OC4FE)OC4FE 0 (OC4PE)OC4PE 0OC4M0 (OC4CE)OC4CE 0 (OC3M_3)OC3M_3 0 (OC4M_3)OC4M_3

Description

capture/compare mode register 2 (output mode)

Fields

CC3S

Capture/Compare 3 selection
OC3FE

Output compare 3 fast enable
OC3PE

Output compare 3 preload enable
OC3M

Output compare 3 mode
OC3CE

Output compare 3 clear enable
CC4S

Capture/Compare 4 selection
OC4FE

Output compare 4 fast enable
OC4PE

Output compare 4 preload enable
OC4M

Output compare 4 mode
OC4CE

Output compare 4 clear enable
OC3M_3

Output Compare 3 mode - bit 3
OC4M_3

Output Compare 4 mode - bit 3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data