ADEN=B_0x0, ADCAL=B_0x0, ADSTART=B_0x0, ADDIS=B_0x0, ADVREGEN=B_0x0, ADSTP=B_0x0
ADC control register
| ADEN | ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0) 0 (B_0x0): ADC is disabled (OFF state) 1 (B_0x1): Write 1 to enable the ADC. |
| ADDIS | ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1â is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing) 0 (B_0x0): No ADDIS command ongoing 1 (B_0x1): Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. |
| ADSTART | ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored. 0 (B_0x0): No ADC conversion is ongoing. 1 (B_0x1): Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. |
| ADSTP | ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1â is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC) 0 (B_0x0): No ADC stop conversion command ongoing 1 (B_0x1): Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. |
| ADVREGEN | ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 0 (B_0x0): ADC voltage regulator disabled 1 (B_0x1): ADC voltage regulator enabled |
| ADCAL | ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing). 0 (B_0x0): Calibration complete 1 (B_0x1): Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. |