STMicroelectronics /STM32G050 /RCC /APBENR1

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Interpret as APBENR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM3EN)TIM3EN 0 (TIM4EN)TIM4EN 0 (TIM6EN)TIM6EN 0 (TIM7EN)TIM7EN 0 (USART5EN)USART5EN 0 (USART6EN)USART6EN 0 (RTCAPBEN)RTCAPBEN 0 (WWDGEN)WWDGEN 0 (USBEN)USBEN 0 (SPI2EN)SPI2EN 0 (SPI3EN)SPI3EN 0 (USART2EN)USART2EN 0 (USART3EN)USART3EN 0 (USART4EN)USART4EN 0 (I2C1EN)I2C1EN 0 (I2C2EN)I2C2EN 0 (I2C3EN)I2C3EN 0 (DBGEN)DBGEN 0 (PWREN)PWREN

Description

APB peripheral clock enable register 1

Fields

TIM3EN

TIM3 timer clock enable

TIM4EN

TIM4 timer clock enable

TIM6EN

TIM6 timer clock enable

TIM7EN

TIM7 timer clock enable

USART5EN

USART5EN

USART6EN

USART6EN

RTCAPBEN

RTC APB clock enable

WWDGEN

WWDG clock enable

USBEN

USBEN

SPI2EN

SPI2 clock enable

SPI3EN

SPI3 clock enable

USART2EN

USART2 clock enable

USART3EN

USART3 clock enable

USART4EN

USART4 clock enable

I2C1EN

I2C1 clock enable

I2C2EN

I2C2 clock enable

I2C3EN

I2C3 clock enable

DBGEN

Debug support clock enable

PWREN

Power interface clock enable

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