STMicroelectronics /STM32G050 /RCC /APBENR2

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Interpret as APBENR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGEN)SYSCFGEN 0 (TIM1EN)TIM1EN 0 (SPI1EN)SPI1EN 0 (USART1EN)USART1EN 0 (TIM14EN)TIM14EN 0 (TIM15EN)TIM15EN 0 (TIM16EN)TIM16EN 0 (TIM17EN)TIM17EN 0 (ADCEN)ADCEN

Description

APB peripheral clock enable register 2

Fields

SYSCFGEN

SYSCFG, COMP and VREFBUF clock enable

TIM1EN

TIM1 timer clock enable

SPI1EN

SPI1 clock enable

USART1EN

USART1 clock enable

TIM14EN

TIM14 timer clock enable

TIM15EN

TIM15 timer clock enable

TIM16EN

TIM16 timer clock enable

TIM17EN

TIM16 timer clock enable

ADCEN

ADC clock enable

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