STMicroelectronics /STM32G050 /TAMP /TAMP_CR2

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Interpret as TAMP_CR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TAMP1NOER 0 (B_0x0)TAMP2NOER 0 (B_0x0)TAMP3NOER 0 (B_0x0)TAMP1MSK 0 (B_0x0)TAMP2MSK 0 (B_0x0)TAMP3MSK 0 (B_0x0)TAMP1TRG 0 (B_0x0)TAMP2TRG 0 (B_0x0)TAMP3TRG

TAMP3TRG=B_0x0, TAMP2TRG=B_0x0, TAMP2MSK=B_0x0, TAMP3NOER=B_0x0, TAMP1TRG=B_0x0, TAMP3MSK=B_0x0, TAMP1MSK=B_0x0, TAMP2NOER=B_0x0, TAMP1NOER=B_0x0

Description

TAMP control register 2

Fields

TAMP1NOER

Tamper 1 no erase

0 (B_0x0): Tamper 1 event erases the backup registers.

1 (B_0x1): Tamper 1 event does not erase the backup registers.

TAMP2NOER

Tamper 2 no erase

0 (B_0x0): Tamper 2 event erases the backup registers.

1 (B_0x1): Tamper 2 event does not erase the backup registers.

TAMP3NOER

Tamper 3 no erase

0 (B_0x0): Tamper 3 event erases the backup registers.

1 (B_0x1): Tamper 3 event does not erase the backup registers.

TAMP1MSK

Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set.

0 (B_0x0): Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection.

1 (B_0x1): Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased.

TAMP2MSK

Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set.

0 (B_0x0): Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection.

1 (B_0x1): Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

TAMP3MSK

Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set.

0 (B_0x0): Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection.

1 (B_0x1): Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased.

TAMP1TRG

Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event.

0 (B_0x0): If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event.

1 (B_0x1): If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event.

TAMP2TRG

Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event.

0 (B_0x0): If TAMPFLT ≠ 00 Tamper 2 input staying low triggers a tamper detection event.

1 (B_0x1): If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event.

TAMP3TRG

Active level for tamper 3 input (active mode disabled) If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection event.

0 (B_0x0): If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event.

1 (B_0x1): If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event.

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