EOSMP=B_0x0, EOCAL=B_0x0, EOS=B_0x0, AWD2=B_0x0, AWD1=B_0x0, CCRDY=B_0x0, ADRDY=B_0x0, EOC=B_0x0, OVR=B_0x0, AWD3=B_0x0
ADC interrupt and status register
| ADRDY | ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 (B_0x0): ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): ADC is ready to start conversion |
| EOSMP | End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1â. 0 (B_0x0): Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): End of sampling phase reached |
| EOC | End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. 0 (B_0x0): Channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Channel conversion complete |
| EOS | End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. 0 (B_0x0): Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Conversion sequence complete |
| OVR | ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. 0 (B_0x0): No overrun occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Overrun has occurred |
| AWD1 | Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. 0 (B_0x0): No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Analog watchdog event occurred |
| AWD2 | Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. 0 (B_0x0): No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Analog watchdog event occurred |
| AWD3 | Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. 0 (B_0x0): No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Analog watchdog event occurred |
| EOCAL | End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. 0 (B_0x0): Calibration is not complete 1 (B_0x1): Calibration is complete |
| CCRDY | Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. 0 (B_0x0): Channel configuration update not applied. 1 (B_0x1): Channel configuration update is applied. |