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STMicroelectronics /STM32G051 /DAC /DAC_SWTRGR

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Interpret as DAC_SWTRGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SWTRIG1 0 (B_0x0)SWTRIG2

SWTRIG2=B_0x0, SWTRIG1=B_0x0

Description

DAC software trigger register

Fields

SWTRIG1

DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.

0 (B_0x0): No trigger

1 (B_0x1): Trigger
SWTRIG2

DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation.

0 (B_0x0): No trigger

1 (B_0x1): Trigger

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data