AWD2CH15=B_0x0, AWD2CH1=B_0x0, AWD2CH8=B_0x0, AWD2CH17=B_0x0, AWD2CH7=B_0x0, AWD2CH6=B_0x0, AWD2CH11=B_0x0, AWD2CH9=B_0x0, AWD2CH4=B_0x0, AWD2CH10=B_0x0, AWD2CH3=B_0x0, AWD2CH16=B_0x0, AWD2CH14=B_0x0, AWD2CH12=B_0x0, AWD2CH18=B_0x0, AWD2CH0=B_0x0, AWD2CH13=B_0x0, AWD2CH2=B_0x0, AWD2CH5=B_0x0
ADC Analog Watchdog 2 Configuration register
| AWD2CH0 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH1 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH2 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH3 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH4 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH5 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH6 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH7 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH8 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH9 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH10 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH11 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH12 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH13 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH14 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH15 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH16 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH17 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |
| AWD2CH18 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD2 1 (B_0x1): ADC analog channel-x is monitored by AWD2 |