TOVS=B_0x0, OVSR=B_0x0, OVSS=B_0x0, CKMODE=B_0x0, OVSE=B_0x0, LFTRIG=B_0x0
ADC configuration register 2
| OVSE | Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Oversampler disabled 1 (B_0x1): Oversampler enabled |
| OVSR | Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): 2x 1 (B_0x1): 4x 2 (B_0x2): 8x 3 (B_0x3): 16x 4 (B_0x4): 32x 5 (B_0x5): 64x 6 (B_0x6): 128x 7 (B_0x7): 256x |
| OVSS | Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): No shift 1 (B_0x1): Shift 1-bit 2 (B_0x2): Shift 2-bits 3 (B_0x3): Shift 3-bits 4 (B_0x4): Shift 4-bits 5 (B_0x5): Shift 5-bits 6 (B_0x6): Shift 6-bits 7 (B_0x7): Shift 7-bits 8 (B_0x8): Shift 8-bits |
| TOVS | Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). 0 (B_0x0): All oversampled conversions for a channel are done consecutively after a trigger 1 (B_0x1): Each oversampled conversion for a channel needs a trigger |
| LFTRIG | Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 (B_0x0): Low Frequency Trigger Mode disabled 1 (B_0x1): Low Frequency Trigger Mode enabled |
| CKMODE | ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). 0 (B_0x0): ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) 1 (B_0x1): PCLK/2 (Synchronous clock mode) 2 (B_0x2): PCLK/4 (Synchronous clock mode) 3 (B_0x3): PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) |