BG=B_0x0, TG=B_0x0, CC1G=B_0x0, COMG=B_0x0, B2G=B_0x0, UG=B_0x0
event generation register
| UG | Update generation This bit can be set by software, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). |
| CC1G | Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 0 (B_0x0): No action 1 (B_0x1): A capture/compare event is generated on channel 1: |
| CC2G | Capture/Compare 2 generation Refer to CC1G description |
| CC3G | Capture/Compare 3 generation Refer to CC1G description |
| CC4G | Capture/Compare 4 generation Refer to CC1G description |
| COMG | Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 0 (B_0x0): No action 1 (B_0x1): When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. |
| TG | Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. |
| BG | Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. |
| B2G | Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. |