CC1S=B_0x0, IC1F=B_0x0, CC2S=B_0x0, IC1PSC=B_0x0
capture/compare mode register 1 (input mode)
| CC1S | Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER). 0 (B_0x0): CC1 channel is configured as output 1 (B_0x1): CC1 channel is configured as input, IC1 is mapped on TI1 2 (B_0x2): CC1 channel is configured as input, IC1 is mapped on TI2 3 (B_0x3): CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| IC1PSC | Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register). 0 (B_0x0): no prescaler, capture is done each time an edge is detected on the capture input 1 (B_0x1): capture is done once every 2 events 2 (B_0x2): capture is done once every 4 events 3 (B_0x3): capture is done once every 8 events |
| IC1F | Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0 (B_0x0): No filter, sampling is done at fDTS 1 (B_0x1): fSAMPLING=fCK_INT, N=2 2 (B_0x2): fSAMPLING=fCK_INT, N=4 3 (B_0x3): fSAMPLING=fCK_INT, N=8 4 (B_0x4): fSAMPLING=fDTS/2, N=6 5 (B_0x5): fSAMPLING=fDTS/2, N=8 6 (B_0x6): fSAMPLING=fDTS/4, N=6 7 (B_0x7): fSAMPLING=fDTS/4, N=8 8 (B_0x8): fSAMPLING=fDTS/8, N=6 9 (B_0x9): fSAMPLING=fDTS/8, N=8 10 (B_0xA): fSAMPLING=fDTS/16, N=5 11 (B_0xB): fSAMPLING=fDTS/16, N=6 12 (B_0xC): fSAMPLING=fDTS/16, N=8 13 (B_0xD): fSAMPLING=fDTS/32, N=5 14 (B_0xE): fSAMPLING=fDTS/32, N=6 15 (B_0xF): fSAMPLING=fDTS/32, N=8 |
| CC2S | Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER). 0 (B_0x0): CC2 channel is configured as output 1 (B_0x1): CC2 channel is configured as input, IC2 is mapped on TI2 2 (B_0x2): CC2 channel is configured as input, IC2 is mapped on TI1 3 (B_0x3): CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| IC2PSC | Input capture 2 prescaler |
| IC2F | Input capture 2 filter |