STMicroelectronics /STM32G061 /TIM2 /SMCR

Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

0 (B_0x0): Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.

1 (B_0x1): Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.

2 (B_0x2): Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.

3 (B_0x3): Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

8 (B_0x8): Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)

OCREF clear selection This bit is used to select the OCREF clear source

0 (B_0x0): OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR

1 (B_0x1): OCREF_CLR_INT is connected to ETRF

Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

0 (B_0x0): Internal Trigger 0 (ITR0)

1 (B_0x1): Internal Trigger 1 (ITR1)

2 (B_0x2): Internal Trigger 2 (ITR2)

3 (B_0x3): Internal Trigger 3 (ITR3)

4 (B_0x4): TI1 Edge Detector (TI1F_ED)

5 (B_0x5): Filtered Timer Input 1 (TI1FP1)

6 (B_0x6): Filtered Timer Input 2 (TI2FP2)

7 (B_0x7): External Trigger input (ETRF)

8 (B_0x8): Internal Trigger 4 (ITR4)

9 (B_0x9): Internal Trigger 5 (ITR5)

10 (B_0xA): Internal Trigger 6 (ITR6)

11 (B_0xB): Internal Trigger 7 (ITR7)

12 (B_0xC): Internal Trigger 8 (ITR8)

Master/Slave mode

0 (B_0x0): No action

1 (B_0x1): The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0 (B_0x0): No filter, sampling is done at fDTS

1 (B_0x1): fSAMPLING=fCK_INT, N=2

2 (B_0x2): fSAMPLING=fCK_INT, N=4

3 (B_0x3): fSAMPLING=fCK_INT, N=8

4 (B_0x4): fSAMPLING=fDTS/2, N=6

5 (B_0x5): fSAMPLING=fDTS/2, N=8

6 (B_0x6): fSAMPLING=fDTS/4, N=6

7 (B_0x7): fSAMPLING=fDTS/4, N=8

8 (B_0x8): fSAMPLING=fDTS/8, N=6

9 (B_0x9): fSAMPLING=fDTS/8, N=8

10 (B_0xA): fSAMPLING=fDTS/16, N=5

11 (B_0xB): fSAMPLING=fDTS/16, N=6

12 (B_0xC): fSAMPLING=fDTS/16, N=8

13 (B_0xD): fSAMPLING=fDTS/32, N=5

14 (B_0xE): fSAMPLING=fDTS/32, N=6

15 (B_0xF): fSAMPLING=fDTS/32, N=8

External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.

0 (B_0x0): Prescaler OFF

1 (B_0x1): ETRP frequency divided by 2

2 (B_0x2): ETRP frequency divided by 4

3 (B_0x3): ETRP frequency divided by 8

External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.

0 (B_0x0): External clock mode 2 disabled

1 (B_0x1): External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

External trigger polarity This bit selects whether ETR or ETR is used for trigger operations

0 (B_0x0): ETR is non-inverted, active at high level or rising edge

1 (B_0x1): ETR is inverted, active at low level or falling edge

Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

0 (B_0x0): Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.

1 (B_0x1): Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.

2 (B_0x2): Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.

3 (B_0x3): Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

8 (B_0x8): Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)

Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

0 (B_0x0): Internal Trigger 0 (ITR0)

1 (B_0x1): Internal Trigger 1 (ITR1)

2 (B_0x2): Internal Trigger 2 (ITR2)

3 (B_0x3): Internal Trigger 3 (ITR3)

4 (B_0x4): TI1 Edge Detector (TI1F_ED)

5 (B_0x5): Filtered Timer Input 1 (TI1FP1)

6 (B_0x6): Filtered Timer Input 2 (TI2FP2)

7 (B_0x7): External Trigger input (ETRF)

8 (B_0x8): Internal Trigger 4 (ITR4)

9 (B_0x9): Internal Trigger 5 (ITR5)

10 (B_0xA): Internal Trigger 6 (ITR6)

11 (B_0xB): Internal Trigger 7 (ITR7)

12 (B_0xC): Internal Trigger 8 (ITR8)