STMicroelectronics /STM32G061 /USART1 /ICR

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Interpret as ICR

Description

Interrupt flag clear register

Fields

PECF	Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
FECF	Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
NECF	Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
ORECF	Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
IDLECF	Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
TXFECF	TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
TCCF	Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
TCBGTCF	Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
LBDCF	LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
CTSCF	CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
RTOCF	Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to pageÂ 835.
EOBCF	End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
UDRCF	SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
CMCF	Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
WUCF	Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to pageÂ 835.

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