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STMicroelectronics /STM32G070 /SPI1 /HWCFGR

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Interpret as HWCFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CRCCFG0I2SCFG0I2SCKCFG 0DSCFG0NSSCFG

Description

hardware configuration register

Fields

CRCCFG

CRC capable at SPI mode
I2SCFG

I2S mode implementation
I2SCKCFG

I2S master clock generator at I2S mode
DSCFG

SPI data size configuration
NSSCFG

NSS pulse feature enhancement at SPI master

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data